Microprocessor based systems operate in a normal mode by fetcning instructions, executing the instructions and routing data between various registers and/or system ports. This occurs within the constraints of various timing cycles called machine cycles, with the flow of data and instructions tracked through the use of various data and program pointers, etc. Since instructions are executed in a sequential format, it is necessary for the central processing unit or microprocessor to know the status of the instruction that is being executed, or the data or instructions that are being transferred, etc. Whenever the system loses track of the program, it is possible to enter an undesirable program loop that the system cannot get out of, which can result in a catastrophic system failure. This sometimes is referred to as deadlocking the system.
Various techniques have been utilized to enable a user of the system to get out of a deadlocked mode such as the use of interrupts, watchdog timer circuits, etc. However, one disadvantage to losing track of where the CPU is in the execution sequence is the possibility of damaging certain internal data stored in internal registers. For example, if an instruction is misinterpreted as loading the contents of the internal data bus into an internal register, this could destroy the contents of the register. The contents of this register may be important to the overall system operation which may require the system to be completely reinitialized.
Therefore, there exists a need for a system that protects internal registers from execution errors. These execution errors may be due to timing factors or the general failure of the system program to properly execute.